This invention relates to a system for storing and processing an array of data-elements, such as pixel data.
In particular, the invention is concerned with such a system which comprises a memory having a plurality of memory locations each having a capacity of a predetermined number B (e.g. 32) bits and a processing means for processing data elements and operable to read the data-elements from and/or write the data elements to the memory.
Although the memory and processing means are capable of dealing with the predetermined number B of bits (e.g. 32), in some applications, the data-elements may have a lesser resolution (e.g. 16 or 8 bits). In such cases, it would be possible to use only 16 or 8 bits of the 32 bits available for each data-element. However, the memory would not then be used to its full capacity. Also, in a demand-paged dual memory system in which pages are swapped from a paging memory into the first-mentioned memory, pages of data-elements would need to be swapped more often than is necessary.
It may therefore be considered expedient to split the whole memory into two for 16-bit data, or four for 8-bit data, and thus overlay whole sub-arrays of the data-elements one on top of another. This would make available the whole capacity of the memory, but would suffer from the disadvantage that severe complications would arise when swapping, for example, just one page of 16-bit or 8-bit data between the memory and paging memory, because it would be necessary to select only half or a quarter of the stored data at each memory location for transfer from the memory to the paging memory, and it would be necessary to mask off half or three-quarters of the memory when transferring a page of data from the paging memory to the first memory.
In order to overcome this problem, in accordance with the invention, the processing means is operable in a mode for processing data-elements having a predetermined number b (e.g. 16) bits not greater than half of said predetermined number B and being operable to read the data-elements from and/or write the data elements to different bit levels (e.g. L(0), L(1)) of the memory locations so that a plurality of data-elements can be stored at such a memory location and so that at no memory location is there stored data-elements from more than one page.
In one embodiment, data elements which are adjacent in at least one direction in the data-array are stored at different bit levels in the memory. However, in a preferred embodiment, the data-elements are stored in the memory in aligned groups of N (e.g. 16) data-elements, and data elements of groups which are adjacent in at least one direction in the data-array are stored at different bit levels in the memory. In this case, in one arrangement, each memory location is divided into two, that is to say, the number b (e.g. 16) of bits of a data-element is half of the number B (e.g. 32) of bits of a memory location, and the data-elements are arranged in patches each of two groups with the data-elements of the two groups being stored at two respective different bit levels (e.g. bits 0-15, bits 16-31). In another arrangement, each memory location is divided into four, that is to say the number b (e.g. 8) of bits of a data-element is a quarter of the number B (e.g. 32) of bits of a memory location, and the data-elements are arranged in patches of four groups with the pixels of the four groups being stored at four respective different bit levels (e.g. bits 0-7, bits 8-15, bits 16-23, bits 24-31). Preferably, the system is operable in at least two modes selected from the divided-into-two mode, the divided-into-four mode, and a mode in which all B of the bits at a memory location are used to stored each data-element. In this case, the memory may be addressed by an address having bits whose significance varies in accordance with the selected mode of operation, and the system may further comprise a funnel shifter which receives the address bits whose significance can change and a mode selection signal and which outputs address bits appropriate to the selected mode and a level signal indicative of the bit level in the memory of the data-element to be accessed.
During reading of the memory the processing means may be operable to read all of the data at a memory location, the system further comprising means for supplying a shift signal dependent on the level signal to the processing means and the processing means may be operable to bit-shift the read data by an amount dependent on the shift signal to that the data-element to be processed occupies predetermined bit positions.
During writing to the memory, in at least said first-mentioned mode the processing means is preferably operable to duplicate the bits to be written at the different levels and the system may comprise means for supplying a partial write-enable signal dependent on the level signal for controlling the memory so that the data-element is written only to the appropriate bit levels of the memory.
In the preferred embodiment, the processing means comprises a plural number N (e.g. 16) of processors equal in number N to the number of data-elements in a group, where the processors are capable of accessing in parallel all of the data-elements of a group. In this case upon reading of a group which is misaligned with respect to an aligned group, the shift signal supplying means is preferably operable to supply to the processors a respective shift signal for each data-element in the misaligned group which is dependent upon the position of the data-element in the group and the misalignment of the group. Also, upon writing of a group which is misaligned with respect to an aligned group, the partial write-enable signal supplying means is preferably operable to supply to the memory a respective partial write-enable signal for each data-element in the misaligned group which is dependent on the position of the data-element in the group and the misalignment of the group.